Integrated circuit development involves the creation of electronic components, such as transistors, resistors, capacitors and the metallic interconnect of these components onto a piece of a semiconductor, such as silicon. A typical standard cell based integrated circuit design cycle involves multiple stages such as system specification, architectural design, functional/logic design, timing analysis, physical design, timing optimization, and fabrication. During the timing analysis and timing optimization stages, statistical SPICE (Simulation Program with Integrated Circuit Emphasis) simulations are typically utilized to assess an integrated circuit's performance and estimated production yield.
Although statistical simulations are often burdensome for large integrated circuit designs, they are virtually intractable for large hierarchical circuit element arrays, such as memory arrays. In large hierarchical circuit element arrays, multiplicity varies greatly among transistors in different blocks. For example, a memory array may include 128 bitcells per sense amplifier, 64 sense amplifiers per control logic block, and 128 control logic blocks. In effect, the memory array includes 128*64*128=1,048,576 bitcells, 128*64=8,192 sense amplifiers, and 128 control logic blocks. The larger the number of copies of a transistor, the farther simulations are likely to reach into the distribution tails of the local, or the random, instance-specific transistor parameters.
To obtain reliable visibility to the distribution tails, a developer requires many millions of simulations of the very large memory arrays. Even a single simulation of the complete array can take several days. As such, the developer may simulate only a critical path in an array. However, selectively skewing transistors in different blocks by different amounts in a statistically accurate manner is not trivial. As such, designers typically skew devices in the different blocks to their individually extreme values to err on the side of safety. Such an approach, however, results in a less competitive design and does not enable designers to assess the robustness of third party IP, which may not have been designed to such pessimistic constraints.